Technical Program Manager (Silicon Programs)
virtual
· Dificultad 3/5
The process typically starts with a recruiter screen emphasizing scope, cross-functional fit, and experience with complex schedules. Candidates then report interviews with a hiring manager and several stakeholders across engineering and operations, focusing on planning rigor, risk management, and communication. Loops often include scenario-based questions around milestone execution, dependency tracking, and escalation strategy across hardware and software teams. Timelines commonly run a few weeks, with decision-making tied to alignment among cross-functional interviewers.
- Describe how you build and maintain an end-to-end silicon program plan across architecture, design, verification, and validation milestones.
- Tell me about a time you resolved conflict between two teams with competing priorities. What was the outcome?
- If a critical deliverable slips and threatens a tape-in or launch milestone, what steps do you take in the first 48 hours?
- How do you ensure transparency and accountability without creating a blame culture on high-pressure programs?
Graphics Driver Software Engineer
virtual
· Dificultad 4/5
The process commonly begins with a recruiter call followed by a technical screen that probes low-level programming, OS concepts, and debugging. Candidates often see a longer virtual loop with multiple engineers, where discussions cover C or C++ depth, concurrency, performance profiling, and GPU pipeline fundamentals. Some teams incorporate a practical exercise, such as analyzing a bug scenario or reasoning through code, even when no formal take-home is required. The overall timeline is frequently a few weeks, and coordination across time zones can extend scheduling.
- Walk through how you would diagnose a GPU hang or TDR-like event and what signals or logs you would collect first.
- Explain common causes of race conditions in driver code and how you would design synchronization to minimize contention.
- Tell me about a time you improved performance or reduced latency in a system-level component. What did you measure and how?
- How do you balance correctness, performance, and maintainability when a change is needed late in a release cycle?
Silicon Design Verification Engineer
virtual
· Dificultad 4/5
The process typically starts with a recruiter screen focused on role alignment, work authorization, and schedule expectations. Candidates report one to two technical phone or video screens that dive into verification fundamentals and prior project depth. A virtual panel loop often follows, mixing SystemVerilog/UVM discussions, debugging scenarios, and behavioral questions with several engineers and a hiring manager. Timelines commonly span a few weeks, with feedback gated by team availability and headcount approvals.
- Explain how you would structure a UVM testbench for a new block and what components you would prioritize first.
- How do you debug an intermittent failure in a constrained-random test and determine whether it is a testbench issue or a design bug?
- Describe a time you found a critical bug late in the cycle. How did you communicate it and drive resolution?
- If coverage is behind schedule, how would you decide what to target next and how would you negotiate tradeoffs with design?