Technical Program Manager (Silicon/Platform)
virtual
· Difficulty 3/5
Candidates report a recruiter screen followed by a hiring-manager interview focused on program scope, stakeholder management, and experience with hardware-software milestones. The process typically includes multiple cross-functional interviews with engineering, product, and operations partners to assess planning rigor, risk management, and execution under schedule pressure. Interview loops often emphasize behavioral and situational prompts grounded in real product-development constraints such as tape-in gates, validation readiness, and dependency tracking. Decisions commonly depend on evidence of driving alignment across functions and communicating status crisply to leadership.
- How do you build and maintain an integrated schedule that spans silicon milestones, firmware readiness, and system validation?
- Tell us about a program that was slipping. What leading indicators did you use, and what actions changed the outcome?
- A critical dependency team is unresponsive and your milestone is at risk. What escalation and alignment steps do you take in the first 48 hours?
- What does effective cross-functional communication look like in a matrixed organization, and how do you adapt your style for engineers versus executives?
Embedded Software Engineer (Modem/Connectivity)
virtual
· Difficulty 4/5
Candidates report an initial recruiter screen followed by one or more technical screens with engineers focused on C/C++, operating systems concepts, and low-level debugging. The process typically includes a virtual interview loop with several engineers, mixing coding questions with system design discussions relevant to drivers, real-time constraints, and concurrency. Some teams emphasize deep dives into prior work on embedded stacks, performance, and memory-constrained environments rather than purely algorithmic puzzles. Final steps may include a manager conversation centered on team fit, cross-functional collaboration, and project execution.
- In C, how would you debug a sporadic crash in a multithreaded service when you only have a core dump and logs?
- Explain how interrupts, deferred work, and scheduling interact in an embedded or kernel environment, and where latency can be introduced.
- Design a thread-safe ring buffer for passing packets between producer and consumer under real-time constraints. What tradeoffs would you make?
- Describe a time you had to align with hardware, QA, and product on a release issue. How did you communicate risk and drive closure?
RF Design Engineer
virtual
· Difficulty 4/5
Candidates report starting with a recruiter phone screen focused on role fit, location, and background in wireless standards and RF fundamentals. The process typically moves to one or two technical video interviews with RF or modem team members covering circuits, RF measurements, and prior project depth. A longer virtual panel is common, with multiple back-to-back interviews that mix whiteboard-style problem solving and deep dives into past designs and tradeoffs. Timelines often span a few weeks depending on team urgency and interview-loop availability.
- Walk through how you would design and validate an LNA for a given noise figure and linearity target, and what measurements you would run to confirm performance.
- Explain the difference between SNR, NF, and EVM, and how each shows up in an RF receiver chain in a cellular system.
- Describe a time a lab result contradicted your simulation. How did you isolate root cause and what changed in the design or test setup?
- If you see intermittent spurs during receiver testing, what is your step-by-step debug plan across board, LO, power, and measurement equipment?