Technical Program Manager, Silicon and IP Delivery
virtual
· Difficulty 3/5
Candidates report a recruiter screen focused on scope of prior programs, stakeholder environments, and comfort with cross-functional hardware schedules. The process typically includes one or more interviews with the hiring manager and program peers covering planning methods, risk management, and communication in a matrix organization. Many loops add cross-functional rounds with engineering or product partners to evaluate how candidates drive alignment and handle ambiguity across IP, verification, and release readiness. Timelines are often a few weeks, and candidates note that clarity around ownership boundaries and decision-making authority can be a key theme in later-stage conversations.
- How would you build and maintain an end-to-end program plan for an IP release with dependencies across design, verification, and software enablement?
- Describe a time you had conflicting priorities from two senior stakeholders. How did you resolve it and what was the outcome?
- What leading indicators would you track to detect schedule risk early in a silicon or IP delivery program?
- What does effective collaboration look like in a partner-driven ecosystem where requirements can evolve late in the cycle?
Software Engineer, Compiler Toolchain (LLVM/GCC)
virtual
· Difficulty 4/5
Candidates report a recruiter screen followed by a technical phone or video interview covering data structures, C or C++, and domain fundamentals relevant to compilers. The process typically continues with a multi-interviewer virtual loop that mixes coding, systems knowledge, and deeper compiler discussions such as optimization, code generation, and debugging. Some teams include a practical exercise around reading unfamiliar code, reasoning about performance regressions, or explaining an approach to a compiler pass. A final stage commonly includes a hiring manager conversation focused on collaboration, prioritization, and alignment with Arm’s engineering culture and partner-driven development.
- Write a function to parse and evaluate a simple expression grammar, and discuss how you would handle errors and edge cases.
- What is SSA form, and why does it make certain optimizations easier?
- A microbenchmark slows down after a compiler change. How would you isolate whether the regression is in instruction selection, scheduling, or inlining decisions?
- How do you balance upstreaming changes to open source with delivering partner-specific requirements on a deadline?
Graduate Hardware Verification Engineer
virtual
· Difficulty 3/5
Candidates report an initial recruiter conversation focused on eligibility, location preferences, and broad fit, followed by a technical screen with an engineer. The process typically includes one or more virtual panel rounds covering digital design fundamentals, verification concepts, and practical problem solving. Some teams add a short coding or debugging exercise (often HDL-oriented) and a behavioral conversation with the hiring manager. Timelines commonly span a few weeks, with variability based on team headcount and interview panel availability.
- Explain the difference between combinational and sequential logic, and how you would avoid creating unintended latches in RTL.
- How would you build a verification plan for a simple bus interface, and what coverage metrics would you track?
- Given a failing test where a counter occasionally skips values, how would you debug it and what signals would you inspect first?
- Describe a time you received tough feedback on your technical work and how you responded.