Just wrapped the Intel senior SWE loop, targeting what maps roughly to their L5 equivalent (Senior Engineer 2). The system design round was the most interesting part so sharing details.
Two system design sessions, 45 minutes each. First one was platform-ish: design a telemetry pipeline that can handle high-throughput sensor data from chipsets running in a distributed manufacturing environment. Nothing crazy, but they cared a lot about fault tolerance and exactly-once delivery semantics. I talked through Kafka, wrote out rough schema, touched on backpressure. Second session leaned more infrastructure: design a distributed key-value store, which is honestly a classic, but they drilled into consistency models. Asked me to compare eventual vs strong consistency, when you'd choose each. I walked through Dynamo-style setup with vector clocks and they pushed back productively on failure modes.
Few things I noticed that differ from FAANG-style system design: They are not looking for you to throw buzzwords. When I dropped "service mesh" without explaining why, the interviewer stopped me and asked me to slow down. They genuinely want to see reasoning, not architecture diagrams. Cross-functional context matters more than I expected. Intel is chip-focused, so when I framed my telemetry design around data coming off physical hardware sensors, the energy in the room shifted. They noticed. One interviewer explicitly said their teams use a mix of legacy enterprise tooling and modern cloud-native, so talking about pragmatic migration paths scored points.
Comfort with C++ came up briefly even though I was applying for a platform role, not embedded. They asked if I had opinions on memory management. I'm a mostly-Go/Python person so I was honest about that; didn't seem to hurt me.
Total loop: phone screen, two coding rounds, two system design, one behavioral, one hiring manager chat. Timeline was about 5 weeks start to finish. Decision came in 8 days after onsite.
Happy to answer specifics if you're prepping.