Just finished my senior SWE loop at Anduril and can share what the system design round actually looked like. Short version: it's harder than Meta's E5 design but less abstract than Google L5. They want real systems, not whiteboard theory.
The prompt I got was design a data pipeline that ingests sensor telemetry from autonomous systems at high frequency. You're expected to think about message queues, partitioning strategy, exactly-once delivery guarantees, and what happens when the downstream consumer is slow. I spent too long on the happy path and the interviewer started pushing on failure modes around minute 20, which felt intentional.
What they emphasized: Trade-off reasoning out loud, not just the answer Latency vs throughput specifically (this is a defense tech company, latency matters a lot) How you'd handle degraded modes (edge network down, sensor offline, etc.) Operational concerns: how do you debug this at 2am
The interviewer was a staff+ eng and asked good questions. Didn't feel like he was reading from a rubric. He pushed back on my Kafka choice and asked why not a custom UDP protocol given the latency constraints. Be ready for that kind of push.
Time was 60 minutes: 5 clarifying, 25 designing, 20 deep-dive + questions. My usual ratio was off because I didn't budget for the deep-dive portion.
If you're prepping: brush up on stream processing (Kafka, Flink, Kinesis are all fair game), distributed tracing, and be ready to talk about CAP theorem in the context of real-time control systems, not just a distributed database. The defense / autonomy context makes the constraint weightings unusual compared to typical FAANG design rounds.
Leveling: they were considering me for L5 (which maps roughly to senior SWE). I was told L5 is expected to own a component end-to-end and contribute to cross-team architecture decisions. Design bar felt appropriate for that.